So far, it's looking pretty good.
We have three 165Mhz (165MSPS) analog-digital-converters in Arsenal chip ("analog front end" in Samsung nomenclature).
Each ADC has three external inputs easily selectable in software (by lld3ChAfe_SetADC[345]Mux(); setting Arsenal I2C register bits directly shouldn't be too hard as well). I guess in European B-Series TVs all those inputs are on: PC/VGA, Component, and Scart1 (Scart2 ?) connectors, respectively.
So, we should be able to (e.g.) supply required H/V sync signals to PC/VGA connector, while capturing samples from Component inputs

.
AFAIK highest resolution available for analog inputs is 1920x1080@60. Pixel clock for this mode is 148.50Mhz, H (total): 2200, H (active): 1920. I believe we can capture pixels from H-sync/H-blank periods as well, perhaps as many as 2196 (2200-4) in total per line. I'm getting somehow promising results with the following settings:
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devmem2 0x309200cc w 0
devmem2 0x309200c4 w 0x894
(0x309200cc: active H position, 0x309200c4: active H size; both registers from Chelsea incapt subsystem).
We will still have ca 0.2% of gaps in the sample data, but I guess it's not that bad for DIY scope..
Unfortunately I don't have any signal generator to confirm this (I simply connected PAL CVBS signal to one of the inputs via 100nF capacitor for preliminary testing).
AFE3 ADCs are 12bit (all 36 bits transmitted digitally from Arsenal to Chelsea), but I think Samsung internal processing in Chelsea is 10bit at best. There are RGB -> YCbCr conversions involved as well, so I would expect 7-8bit final resolution for result "samples".
Fortunately, internal processing seems to be performed in 4:4:4 YCbCr format for VGA input (which is a nice surprise actually, because it's apparently 4:2:2 for HDMI inputs !!!).
Expected usable frequency range should be ca 100Hz ... 50Mhz (148.50/2.5, a little FFT magic might be required above 30Mhz or so).
Also, for best results, I think we need to disable Samsung
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Fine Clamp, Offset and Gain Control
for AFE3. Hopefully it should be possible with one or more of the following functions:
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lld3ChAfe_SetEqualMargin
lld3ChAfe_SetGvsMode
lld3ChAfe_SelCoast
lld3ChAfe_SetResgMg
lld3ChAfe_SetMvEnd
lld3ChAfe_SetMvSt
lld3ChAfe_SetEqEnd
lld3ChAfe_SetEqStart
lld3ChAfe_SetMvEvent
lld3ChAfe_SetGhsMode
lld3ChAfe_SetVcntMG
lld3ChAfe_SetHcntMG
lld3ChAfe_SetSMCE
lld3ChAfe_SetSMCEClear
lld3ChAfe_SetSMCEThr
lld3ChAfe_SetClampSel
lld3ChAfe_SetGhsExtMode
lld3ChAfe_SetGvsPriority
lld3ChAfe_SetGvsExtMode
lld3ChAfe_SetAdcClampLength
lld3ChAfe_SetAdcClampStart
lld3ChAfe_SetUpCounterReference
lld3ChAfe_SetGhsMargin
lld3ChAfe_SetSogMg
lld3ChAfe_SetNoVSyncDetTime
lld3ChAfe_SetSyncDetTime
lld3ChAfe_SetSogSel
lld3ChAfe_SetSogModExt
lld3ChAfe_SetSogModSel
lld3ChAfe_SetCompModSel
lld3ChAfe_SetVoltageClamp
lld3ChAfe_SetAclpTarget
lld3ChAfe_SetRcrClpTarget
lld3ChAfe_SetBcbClpTarget
lld3ChAfe_SetGyyClpTarget
lld3ChAfe_SetClpSel
lld3ChAfe_SetManLevel
lld3ChAfe_SetAddBle
lld3ChAfe_SetAddSte
lld3ChAfe_SetExtHsEdge
lld3ChAfe_SetVsUse
lld3ChAfe_SetAclpSpeed
lld3ChAfe_SetAvFloorEn
lld3ChAfe_SetReduceAccGainEn
lld3ChAfe_SetManSlice
lld3ChAfe_SetUseClpUdp
lld3ChAfe_SetI2cEnable
lld3ChAfe_SetSdpmode
lld3ChAfe_SetSliceSelection
lld3ChAfe_SetCsPos
lld3ChAfe_SetTpgnPattern
lld3ChAfe_SetTpgnEn
lld3ChAfe_SetOutDataBypass
lld3ChAfe_SetOutRbSwap
lld3ChAfe_SetOutHsMode
lld3ChAfe_SetOutVsMode
lld3ChAfe_SetClampPcSel
lld3ChAfe_SetClampControlSignal
lld3ChAfe_SetExtHSyncSel
lld3ChAfe_SetCkPhaseSel
lld3ChAfe_SetBypassSel
lld3ChAfe_SetSogBw
lld3ChAfe_SetVhstVal
lld3ChAfe_SetVlcPc3
lld3ChAfe_SetVlcPc2
lld3ChAfe_SetCurrentHsComp
lld3ChAfe_SetThrVolHsComp
lld3ChAfe_SetPcgMuxSel
lld3ChAfe_SelectDllOut
lld3ChAfe_SetSsVth
lld3ChAfe_Set3ChVoltageRefRange
lld3ChAfe_SetData
lld3ChAfe_SetVcoRange
lld3ChAfe_SetMainDivider
lld3ChAfe_SetPllPol
lld3ChAfe_SetPllBandWidth
lld3ChAfe_SetPowerDownPC3
lld3ChAfe_SetPowerDownPC2
lld3ChAfe_SetPowerDownPC1
lld3ChAfe_SetPowerDownSS
lld3ChAfe_SetADC5Mux
lld3ChAfe_SetADC4Mux
lld3ChAfe_SetADC3Mux
lld3ChAfe_SetDllOut
lld3ChAfe_SetDllBw
lld3ChAfe_SetEnTun
lld3ChAfe_SetCurrentClamp
lld3ChAfe_SetAdcCurrentControl
lld3ChAfe_SetHsPhase
lld3ChAfe_SetDEEn
lld3ChAfe_SetPreOffset_Cr
lld3ChAfe_SetPreOffset_Cb
lld3ChAfe_SetCoeffMatrRcr
lld3ChAfe_SetCoeffMatrBcb
lld3ChAfe_SetCoeffMatrGy
lld3ChAfe_SetOffset_B
lld3ChAfe_SetOffset_G
lld3ChAfe_SetOffset_R
lld3ChAfe_SetInMode
lld3ChAfe_SetTPGNForQpi
lld3ChAfe_Set3chAfe
lld3ChAfe_SetEnNoSync
lld3ChAfe_SetNoSyncTPGN